Multiple electronic devices, such as computers, for example, are often connected together to form networks. When connected to a network, each computer typically includes transmitter/receiver interface circuitry, such as a network interface controller (NIC), which allows data to be transferred to or from the computer. In the case of data reception, the data being received by the computer is typically stored in non-contiguous buffers located in memory, such as random access memory (RAM), for example. Such data is generally stored in the buffers until it can be processed by the computer's central processing unit (CPU), at which time new data may be written to the buffers.
As the speed and size of data transfer continues to increase, it is becoming increasingly more difficult to quickly and efficiently write received data to memory buffers while keeping track of the addresses at which the data is stored. Typical receiver interface circuits use linked list receiver queues stored in RAM for this purpose. One example of such a prior art design is the 82596 Ethernet controller from the Intel Corporation of Santa Clara, Calif. In this design, buffer descriptors are built in RAM and then linked into a linked list. The receiver interface circuitry follows the linked list and uploads the buffer information from RAM to find the next available buffer.
Another prior art example may be found in U.S. Pat. No. 5,990,404 to Delp et al. entitled “Method and Apparatus for Enhanced Scatter mode Allowing User Data to be Page Aligned.” The patent is directed to an adapter to be coupled between a data communications network and a memory. A data packet including protocol header bytes is received from a data communications network by the adapter. A variable amount of data is specified for a first scatter page that contains protocol header bytes. Subsequent sequential pages from the received data packet are transferred by direct memory access (DMA) operations to real page addresses in the memory, with the sequential pages transferred being page aligned in the memory.
Moreover, a page address is written to a DMA list stored in an adapter memory for the sequential pages transferred. A count value is incremented in a packet header of a number of pages transferred for each sequential page transferred. Responsive to transferring a last page from the received data packet, the first scatter page containing the packet header, the DMA list and the protocol header bytes is transferred to a separate address space in the memory.
One drawback of such prior art approaches is that the list of buffer addresses is at some point stored in the system memory (i.e., RAM) of the computer. As a result, the receiver interface circuit must frequently download the address information from the RAM to determine which buffer locations are available for new data being received. The penalty for such data copying increases as the data transfer speed increases. Such prior art devices may therefore not provide adequate performance when used with high speed data sources, such as may be found in Fibre Channel architectures, for example.